ABSTRACT–Power outputs, 3) realization of charging/ discharging

ABSTRACT–Power consumption plays a major
role in present day VLSI design technology. The demand for low power consuming
devices is increasing rapidly and the adiabatic logic is becoming a great
solution. This paper presents an
implementation of adiabatic logic in CMOS with comprehensive analysis and
evaluation of static adiabatic logic circuits
where the current flow through the circuit is controlled such that the energy
dissipation due to switching and capacitor dissipation is minimized. The static
adiabatic logic has an advantage in the form of reduction in switching energy
while comparing with the dynamic adiabatic logic. This advantage is realized
due to the fact that the discharging operation at a node happens only when the
input signal transition demands a change in the state of the output.

 

Keywords—Adiabatic logic,
low power, CMOS, power consumption, dynamic adiabatic logic.

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I.           
INTRODUCTION

 

In recent years,
the demand for battery operated portable products, hand held devices and
wireless communication systems have grown significantly 1. This requires the
VLSI designers to have low power consumption as an important parameter to be
considered while designing digital integrated circuits. Adiabatic switching is
one of the promising approaches among the various non-conventional low power
design methodologies. They work based on the principle of energy recovery from
the circuit nodes, rather than allowing the charge to dissipate from the node
to ground. The energy recovery circuits are broadly classified into fully
adiabatic and quasi adiabatic circuits. Former has asymptotically zero energy
consumption with complex circuit structure 2. On the other hand, the quasi
adiabatic circuits are less complex and incur both adiabatic and non -adiabatic
losses. The structure and operational complexity, such as 1) the number of
operating power-clock phases, 2) single/dual rail outputs, 3) realization of charging/
discharging path and 4) reversible and irreversible of logic styles differ from
one other 3. Most of the energy recovery circuits 4-7 in the literature
are dynamic in nature i.e. the output node charges and discharges for every
clock cycle irrespective of the input signal. Hence, they suffer from the
drawbacks of 1) higher switching activity in output nodes, 2) multiphase and
multiple clock generation and clock signal distributions across the circuit and
3) the existence of differential signaling that adds to the signal overhead.

Adiabatic logic
is an implementation of reversible logic in CMOS where the current flow through
the circuit is controlled such that the energy dissipation due to switching and
capacitor dissipation is minimized 4. This is accomplished by recycling
circuit energy rather than dissipating it into the surrounding environment.
This is beneficial for CMOS implementations, since the input and output charges
are kept separate, with the objective of reduction of leakage power and leakage
current. Adiabatic logic implementations of CMOS have been used to improve
power consumption in comparison to pass transistor logic 5. Adiabatic logic
requires the use of ramp functions instead of the faster switching achieved in
step functions.

The main contributions of the circuit can be listed as follows: 1)
the high on-chip voltage achieved from a 1.2 V supply; 2) the digitally
programmable output voltage; 3) the design for a small area, such that it is
amenable to tight integration with MEMS; 4) the fast rise and fall times in the
microseconds range to allow for sufficiently fast actuation (i.e., MEMS
typically operate in the sub millisecond or millisecond range); 5) the improved
power consumption through the use of a variable frequency clock; and 6) the
integrated discharge stage immune to breakdown at the output for fast discharge
of the MEMS capacitive load.

 

This paper is organized as follows. Section II provides the
general concept of CMOS logic, Section III describes about adiabatic logic,Section
IV describes the techniques under this logic,Section V provides a conclusion.

 

                                                                                                                                                      
II.           
CMOS LOGIC

 

Power dissipation
in conventional CMOS circuits primarilyoccurs during device switching. When the
logic level in the system is “1,” there is a sudden flow of current through channel
resistanceR. Q = CLVdd is the charge supplied by the positive power supply rail
for charging CL to Vdd. CL is the node capacitance , which is referred to as
the load capacitance. Hence, the energy drawn from the power supply is Q.Vdd =
CLV2dd 6. If it is assumed that the energy drawn from powersupply is equal to
that supplied to CL, the energy stored in CLbecomes one half the supplied
energy, i.e. Estored=(½) CL
Vdd2  the
remaining energy is dissipated in R. The same amount of energy is dissipated
during discharging in the NMOS network when the logic level in the system is
“0.” Therefore, the total amount of energy dissipated as heat during charging
and discharging is given by:

 

                        E charge + E discharge
= CL Vdd2

 

From the above
equation, it is apparent that the energy consumption in a conventional CMOS
circuit can be reduced by scaling Vdd and/or CL down. By decreasing the
switching frequency in the circuit, the power 
consumption(P=dE/dT) gets suppressed proportionally 7. Here, the load
capacitance (CL) is charged by a constant current source (I).

 

Conventional
Logic Switching

 

In conventional
CMOS level-restoring logic which uses the constant voltage source Vdd, the
switching event of circuits with rail-to-rail output voltage swing causes an
energy transfer from the power supply to the output node or from the output
node to the ground.

 

                                                                       

Fig.1. Conventional CMOS Charging
and Discharging

During a 0-to-VDD
transition of the output, the total output charge Q= CL VDD is drawn
from the power supply at a constant voltage. Thus, energy E = CL VDD2is
drawn from the power supply during this transition. Charging the output node
capacitance to the voltage level VDD means that at the end of the transition,
the amount of stored energy in the output node is E = ½ CL VDD2.Thus,
half of the injected energy from the power supply is dissipated in the PMOS
network while only one half is delivered to the output node 3. During a
subsequent VDD-to-0 transition of the output node, no charge is drawn from the
power supply and the energy stored in the load capacitance is dissipated in the
NMOS network. To reduce the dissipation, the circuit designer can minimize the
switching events, decrease the node capacitance, reduce the voltage swing, or
apply a combination of these methods.

 

                                                                                                                
III.           
DESCRIPTION OF ADIABATIC LOGIC

 

Principle of
Adiabatic Logic                          

Implementation of
the adiabatic logic on a circuit reduces the power by reusing the stored energy
from thecircuit nodes. Thus, the term adiabatic logic is used in low-power VLSI
circuits, where the energy recovery from the circuit nodes is made possible.
The power clock plays an important role in the adiabatic circuits. Each phase
of the power clock guides the operation of each stage of the adiabatic circuit.
The basic characteristics of the adiabatic circuits which realize no or very
little power dissipation are the following: 1) Never turn on the
transistor when there is a voltage across its drain and source (VDS >
0), 2) The second rule is to never turn off a transistor device, if there
is a current flowing through it at any point of time (IDS _ 0) and 3)
Never pass the current through a diode which form part of the adiabatic logic.
The adiabatic circuits reclaim the energy during their recovery phase, i.e.,
when the nodes are discharging from their charged state. Hence, this logic
helps to reduce the overall power and energy dissipation of the circuits.
Inclusion of such an adiabatic logic in the memory cell design will save
considerable amount of power in the high density systems. Several adiabatic
logic circuits powered by trapezoidal power clocks have been presented in the
literature2. The widely used power clocks exhibit four different phases, named
as evaluate, hold, recover and wait or idle phase.

 

Switching characteristics

 

The power
consumption of the electronic devices can be reduced by adopting different
design styles. Adiabatic computation has been widely studied as a low – power
design technique. To increase the energy efficiency of the logic circuits, the
circuit topology and the operating principles have to be modified as per the
need arises. The amount of energy recycling 1 achievable using adiabatic
techniques is also determined by the process technology, switching speed, and
the voltage swing. This circuit can be modified to recover signal energy by
utilizing ramped power-clock signals instead of static operating voltage and
ground.

 

Constant current
source is used,

i(t)=c dV/dt =c
Vdd/T (1)

 

Energy during
charging

E=( I2*R)*Tramp
(2)

 

The voltage
across the switch = I*R

Q=CL*Vdd ,

I = (CL
*Vdd)/Tramp

 

Eadiabatic=(
I2*R)*Tramp (3)

Therefore

Eadiabatic=R*
C2 * Vdd2/Tramp

 

Where,

E – Energy dissipated during
charging time

Q – Charge transferred to the load

CL – the value of the load
capacitance

R – on resistance of the PMOS
switch

Vdd – the final value of the
voltage at the load

Tramp – is the
charging time

                                                                                                                  
IV.           
TECHNIQUES IN ADIABATIC
LOGIC

 

a.       
LOGIC STRUCTURES

Adiabatic logic
structures are mainly of two types:

 

1.       
Partially adiabatic logic, which is
classified as Efficient charge recovery logic (ECRL), Quasi Adiabatic
Logic(QAL) , Positive feedback adiabatic logic (PFAL), NMOS energy recovery
logic, True single phase adiabatic logic (TSAL)

 

2.       
Fully adiabatic logic, Classified as
Pass transistor adiabatic logic, 2 Phase adiabatic Static CMOS logic (2PASCL),
Split rail charge recovery logic (SCRL)

 

1.1. ECRL

The logic
function in efficient charge recovery logic structure is estimated by pairs of
pull down devices

(NMOS) also
through PMOS device, ECRL is not able to pick up the power clock which performs
like quasi adiabatic logic style. ECRL implements a technique of performing
simultaneous pre-charge and evaluation.

                                                               

                             FIG1.1 ECRL
INVERTER

·        
 Logic function in ECRL inverter is, when power
clock goes up starting from zero to VDD, output stays in ground level and when
power clock reaches at VDD, outputs ‘out’ and ‘/out’ hold logic value zero and
VDD respectively. This output values will be used for the next stage.

·        
When
power clock falls from VDD to zero, ‘/out’ returns its energy to power clock
which recovers the delivered charge.

 

1.2. PFAL

The logic level
degradation is avoided in positive feedback adiabatic logic by latch which was
created with help of two PMOS and two NMOS devices. Similar to ECRL, the logic
function in PFAL is determined by NMOS devices but connected parallely with
PMOS devices. Advantages of PFAL is transmission gate formation, positive and
negative ouput generated through the functional blocks.

 

                                                 

FIG1.2
PFAL INVERTER

·        
Logic
function in PFAL is, when power clock goes up from zero to VDD, output (out)
stays at ground level and /out follows power clock. When power clock arrives at
VDD, out and /out hold logic value zero and VDD. This output values can be used
for the next stage.

·        
 When power clock falls from VDD to zero, /out
returns its energy to power clock which recovers delivered charge.

 

1.3. SCRL

A conventional,
stastic, logic structure does not need dual rail input. It is possible to build
asymptotically zero power CMOS using this technique and ‘Split-Level Charge
Recovery Logic'(SCRL) based inverter is shown in below circuit .Two phase
power-clock supplies are implemented here, where power clock, input and ouput
voltage are at a voltage of VDD/2 when inverter is in idle condition.

                                                                         

FIG1.3
SCRL INVERTER

b.       STATIC ADIABATIC LOGIC FAMILIES

A.      Inverter Circuits

 

The inverter
circuits for QSERL, CEPAL, ASL and QSECRL in figThe comparison of all the
static adiabatic circuits in terms of number of clock per phase, number of
transistors used and the floating node output is listed in Table I. The static
adiabatic circuits are powered by sinusoidal power clock signal. Power clock
(PC) consists of evaluate and hold phase. During the evaluate phase, the new
output is computed and it charges or discharges. The energy is supplied to the
circuit and recovered back by the PC and PCBAR. During hold phase, the output
remains the same. The input is allowed to change during hold phase and it has
to be maintained constant during evaluate phase.

 

 

B.      
Quasi-inverter circuits

Quasi inverter is
a partially adiabatic logic inverter in which shown below circuit has pulsed
power clock supply instead of DC supply like CMOS inverter shown first. Compare
with conventional logic this adiabatic logic inverter gives reduced power
dissipation of 6.37E-20w.

 

                                                                                                                                                     
V.           
CONCLUSION

In
this paper,
it has been observed that, Adiabatic CMOS circuits can be successfully used to
implement a digital circuit design using gradually rising and falling
power-clock. The static adiabatic circuits prove to hold advantage over their
dynamic counterparts, namely, the quasi-adiabatic circuits found in the
literature, in terms of their reduced switching. The adiabatic circuit design
can be improved by introducing conventional power supply. Further to improve
switching speed of adiabatic circuit as compare to CMOS logic new adiabatic
circuits with better switching speed can be designed.

 

                                                                                                                                                    
VI.           
REFERENCES

 

1. MinakshiSanadhya1
,M.Vinoth Kumar2,SRM University – NCR Campus,”Recent Development in
Efficient Adiabatic Logic Circuits and Power Analysis with CMOS Logic”.Modinagar, Ghaziabad.

 

2. P.Sasipriya1,V.S.
Kanchana Bhaaskaran2VIT University, “Two Phase Sinusoidal Power Clocked
Quasi-Static Adiabatic Logic Families”. School of Electrical Engineering VIT
University, Chennai, India.

 

3. Baris Cagdaser 1, Member IEEE
and Bernhard E. Boser 2, Fellow IEEE,2012 “Low-Voltage Electrostatic Actuation
With Inherent Position Feedback”.

4. Banibrata Mukherjee 1, K B M
Swamy2 , Sougata Kar3 , Siddhartha Sen 4,2011″Effect of Voltage Induced
Electrostatic Forces on MEMS Capacitive Accelerometer”, Department of
Electrical Engineering Indian Institute of Technology, Kharagpur-721302, India.

5. Ma Li Ya#1, Anis Nurashikin
Nordin#2, Norhayati Soin#3, 2013 “Design and Analysis of a Low-Voltage
Electrostatic Actuated RF CMOS-MEMS Switch” ,Electrical and Computer
Engineering  Departmen International
Islamic University Malaysia 53100 Kuala Lumpur, Malaysia.

6. 1Padarthi Sindhuja , 1Vinay
Sharma, 2Madhur Deo Upadhayay, 2Atul Vir Singh,2016 “Simulation and Analysis
of Actuation Voltage of Electrostatically Actuated RF MEMS Cantilever and Fixed
– Fixed Switches with Variable Beam Parameters” Department of Electrical
Engineering Shiv Nadar University Gautam Buddha Nagar , India.

7. Enoch
Amoatey Tetteh#1, Mercy Adusei Boatemaa#2 , Eric Ofori Martinson#3,2014 “A
Review Of Various Actuation Methods In Micropumps For Drug Delivery
Applications” Department of Electronics And Communication Engineering ,All
Nations 

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